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30 lines
1.4 KiB
XML
30 lines
1.4 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE pkgmetadata SYSTEM "https://www.gentoo.org/dtd/metadata.dtd">
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<pkgmetadata>
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<maintainer type="person">
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<email>vowstar@gmail.com</email>
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<name>Huang Rui</name>
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</maintainer>
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<upstream>
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<remote-id type="github">YosysHQ/yosys</remote-id>
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</upstream>
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<longdescription lang="en">
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This is a framework for RTL synthesis tools. It currently has extensive
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Verilog-2005 support and provides a basic set of synthesis algorithms
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for various application domains.
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Yosys can be adapted to perform any synthesis job by combining the
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existing passes (algorithms) using synthesis scripts and adding
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additional passes as needed by extending the yosys C++ code base.
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Yosys is free software licensed under the ISC license (a GPL compatible
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license that is similar in terms to the MIT license or the 2-clause BSD
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license).
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</longdescription>
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<longdescription lang="zh">
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这是一个针对RTL合成工具的框架。它目前广泛支持Verilog-2005，并提供一套
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基础的合成算法用于多种应用领域。Yosys可以通过组合现有的合成脚本中的算法，
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并根据需要扩展Yosys的C++代码库来添加额外的算法，从而适应任何合成任务。
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Yosys是根据ISC许可证发布的免费软件，这是一种与GPL兼容的许可证，其条款与
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MIT许可证或二条款BSD许可证类似。
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</longdescription>
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</pkgmetadata>
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